An electronic device may be designed to sustain a maximum level of power dissipation over a given period of time. In many cases, the device may be rated for a continuous average power dissipation as well as a short-term, peak power dissipation. In this disclosure, the continuous average power-dissipation rating is referred to as the thermal design power (TDP), and the peak power-dissipation rating is referred to as the electronic design power (EDP). An electronic device may be damaged when TDP is exceeded for an extended period of time, or when EDP is exceeded for even a short period of time. Accordingly, components that distribute power in the device must be rated for TDP over the long term and EDP over the short term.
Due to the principle of thermal inertia, EDP may be significantly greater than TDP. In one non-limiting example, a digital processor for mobile computing may have a TDP corresponding to 4.5 amperes (A) at a given power-supply voltage, but an EDP corresponding to 9 A at the same power-supply voltage. This presents a practical disadvantage in that the power-handling components of the device—the battery, power transistors, inductor, etc.—which sink no more than 4.5 A on average, must also be configured to handle up to 9 A for periods of, perhaps, microseconds.
The inventor herein has observed that power-handling components robust enough to survive current transients at a higher EDP may significantly increase the size and cost of an electronic device rated for a lower TDP, especially in the high-speed computing arena. Accordingly, a series of approaches will now be disclosed which uses the principle of dynamic voltage-frequency scaling (DVFS) to push the EDP of an electronic device closer to TDP, and thereby reduce the degree of overdesign required for high-current transients.